1. Field of the Invention
The present invention relates to methods and apparatus for testing of mixed-signal VLSI devices.
2. The Prior Art
Digital integrated circuit (IC) devices are typically tested by applying to pins of the device a pattern of binary stimulus signals in predetermined patterns and timing relationships. The digital test system looks at the resulting digital output signals of the device and compares them to a pre-defined truth table. A pass or fail decision results, depending on whether the bits (1's and 0's) at the device's output pins match the bits of the truth table during each time interval. Test systems for such devices are flexible and programmable to suit the requirements of the type of device to be tested. An example of a high-speed, programmable digital test system is the ITS 9000 FX system commercially available from Schlumberger Technologies, San Jose, Calif.
Other devices to be tested are not purely digital. These devices, known as "mixed-signal" devices, can have both digital and analog signal characteristics. Mixed signal devices often are mostly digital, but cannot be tested as purely digital devices are tested. Mixed signal devices can have pins which require one or more analog signal inputs (e.g., analog-to-digital converters (ADC's)) or one or more analog signal outputs (e.g., digital-to-analog converters (DAC's)) in addition to digital-signal inputs or outputs. Mixed signal devices can have pins which receive or supply digital representations of analog signals (e.g., coder-decoder devices (codecs)). Digital representations of analog signals differ from digital signals in that information encoded in digital form represents analog values. It is not enough to compare output bits of the encoded signal to a pre-defined truth table within a time window, because it is the information encoded in the 1's and 0's which must be evaluated to determine whether the device is operating as it should. The encoded signal may be in the form of serial data on a pin or parallel data on multiple pins, and may be encoded using any of a variety of schemes. In addition to testing direct-current (DC) characteristics of the device, the tester must recognize as acceptable any number of different bit combinations which represent essentially the same analog value within some error band. To analyze the output of the DUT, digital signal processing is used to extract quantitative performance parameters from the analog and digital output signals.
Testing of mixed-signal devices is time-consuming. An individual test cycle may consist of applying a set of input stimuli to the device and measuring the response of the device. For example, an analog voltage is applied to an ADC and the resulting digital output is detected. The test cycle is repeated for many different sets of stimuli to evaluate the performance of the device under various conditions. For example, analog voltages are applied to an ADC over its expected range of operation. If the signal-to-noise ratio of the measurement is low, multiple test cycles may have to be performed for each set of input stimuli and the results averaged. Repeatability of device performance may also need to be tested, requiring still more test cycles.
The stimuli to apply to the DUT often depend on its response to stimuli applied in a previous test cycle. Post-processing must therefore be done quickly if the overall test time is to be kept within reason.
Conventional mixed signal test systems are known in which a single host computer controls the overall test process and also performs digital signal processing for multiple analog channels. Data from multiple sources is processed synchronously with a main test program. In some test systems the host computer is augmented by an array processor or digital signal processor. Even if fast Fourier transform (FFT) processing is performed in each analog channel, test systems in which computing resources are shared by the channels have inherent drawbacks. First, a large quantity of information must pass through each analog channel which supplies signals to or receives signals from the DUT. Signals from the DUT are digitized and captured in memory in the channel. This large quantity of data must be transferred via a bus to the shared processor before post-processing can begin. This data-transfer delay becomes significant when multiplied by the number of channels and by the number of test cycles to be performed on the DUT. Second, transferring the data over a common bus to the shared processor must be done channel-by-channel in sequence. Data is then post-processed in the shared processor and/or array processor channel-by-channel in sequence. Sequential transfer and processing likewise impose a throughput delay. Testing speed is limited by the architecture of the test system.
In addition, prior art systems have a single program "thread"--the main program. That is, the main program performs the capture and then the post-processing of data through the shared processor. Processes forked off to a shared array processor or DSP do not run in parallel with the main program. Hence the DSP engine is not utilized in an optimal manner in the prior-art systems because the system does not allow truly asynchronous control of the DSP engine.
Mixed signal devices which handle both analog and digital signals have greater functionality, performance and speed than ever. These devices must be tested as a system, in their working order, with combined testing of digital and analog circuitry including DC characteristics. To test a mixed signal device as a system, the generation and measurement of analog and digital signals, input to and output from the device, require flexible synchronization. The testers available are not adequate to provide synchronous and asynchronous control of mixed signal devices. Faster and more flexible test systems for mixed-signal devices are desired.